1. Field of the Invention
The present invention generally relates to methods of designing semiconductor integrated circuits and semiconductor integrated circuits designed by such methods, and particularly relates to a method of designing a physical block in the hierarchical designing of semiconductor integrated circuits and to a semiconductor integrated circuit designed by such method.
2. Description of the Related Art
In the designing of semiconductor integrated circuits, the delay of each wiring and each gate needs to be identified in order to calculate overall delays by simulation. The delay of wiring has been becoming a predominant factor affecting overall delays as semiconductor integrated circuits are implemented through increasingly fine layouts. It thus becomes necessary to obtain accurate delays by extracting an effect of cross-talk and capacitance between wiring lines from information about wiring intervals.
As the scale of semiconductor integrated circuits increases, a flat design method that determines the layout of an entire circuitry at once may encounter a problem in that data size exceeds the processing limits of design tools. In consideration of this, a hierarchical designing method that determines the layouts of physical blocks divided on a function-by-function basis and combines these layouts is now more often used than before.
In the hierarchical designing method, layouts are determined separately for each physical block. When an effect of cross-talk and capacitance between wiring lines are to be estimated by focusing attention on the outside of a physical block, wiring patterns inside this physical block are not known. Thus, an assumption is made that no wiring pattern is in existence inside the physical block, or that a wiring pattern exists close to the border inside the physical block, thereby allowing an effect of cross-talk and capacitance between wire lines to be extracted. By the same token, when attention is focused on the inside of a physical block, wiring patterns outside this physical block are not known. Thus, an assumption is made that no wiring pattern is in existence outside the physical block, or that a wiring pattern exists close to the border outside the physical block, thereby allowing an effect of cross-talk and capacitance between wire lines to be extracted.
A related art (Patent Document 1) teaches a method of producing macros that can suppress the variation of characteristics such as signal delays caused by cross-talk noise. In this method, an area where chip-level wiring lines can pass through is identified in a macro, and wire lines are automatically laid out inside the macro based on the wiring conditions of the identified area, thereby generating a macro library including information about passing-line assignable areas and automatic wiring line layouts. This allows chip-level wiring lines to pass through the passing-line assignable areas, thereby suppressing cross-talk between inside-macro wiring lines and chip-level wiring lines.
[Patent Document 1]
Japanese Patent Application Publication No. 2002-024310